CONFIG 16. 8.
WIDTH 23.

TREE "PMIC Info, **NOTE** DO NOT OPEN IT WHEN SYSTEM IS RUNNING"
TREE "ONLY SUPPORT BY EAXI, PLEASE DO NOT OPEN BY EAHB OR CPU"
SGROUP "PMIC"
	VARX 0x00 %l ADI.READ(0x8C00)
	TEXTLINE ""
	LINE.LONG 0x00 " CHIPID LOW , PMIC CHIPID LOW"
SGROUP
	VARX 0x04 %l ADI.READ(0x8C04)
	LINE.LONG 0x04 " CHIPID HIGH , PMIC CHIPID HIGH"

TREE "2731"
SGROUP
	VARX 0x08 %l ADI.READ(0x8C54)
	TEXTLINE ""
	LINE.LONG 0x08 " DCDCCPU0 , DCDC_ARM0_VOL"
	BITFLD.LONG 0x08 5.--9.   "  CTRL , DCDC_ARM0_CTRL"
	BITFLD.LONG 0x08 0.--4.   "  CAL , DCDC_ARM0_CAL"
	VARX 0x0C %l ADI.READ(0x8C64)
	TEXTLINE ""
	LINE.LONG 0x0C " DCDCCPU1 , DCDC_ARM1_VOL"
	BITFLD.LONG 0x0C 5.--9.   "  CTRL , DCDC_ARM1_CTRL"
	BITFLD.LONG 0x0C 0.--4.   "  CAL , DCDC_ARM1_CAL"

	VARX 0x10 %l ADI.READ(0x8C28)
	TEXTLINE ""
	LINE.LONG 0x10 " SW PD , POWER_PD_SW"
	BITFLD.LONG 0x10 13.   "  DCXO , LDO_DCXO_PD"
	BITFLD.LONG 0x10 12.   "  SRAM , LDO_SRAM_PD_SW"
	TEXTLINE "                                "
	BITFLD.LONG 0x10 11.   "    RF , DCDC_RF_PD"
	BITFLD.LONG 0x10 10.   "   EMM , DCDC_EMM_PD"
	BITFLD.LONG 0x10 9.    " CLK6M , DCDC_TOPCLK6M_PD"
	TEXTLINE "                                "
	BITFLD.LONG 0x10 8.    "   GEN , DCDC_GEN_PD"
	BITFLD.LONG 0x10 7.    "   MEM , DCDC_MEM_PD"
	BITFLD.LONG 0x10 6.    "  CORE , DCDC_CORE_PD"
	TEXTLINE "                                "
	BITFLD.LONG 0x10 5.    "   GPU , DCDC_GPU_PD_SW"
	BITFLD.LONG 0x10 4.    "  CPU0 , DCDC_ARM0_PD"
	BITFLD.LONG 0x10 3.    "  CPU1 , DCDC_ARM1_PD"
	TEXTLINE "                                "
	BITFLD.LONG 0x10 2.    "  AV18 , LDO_AVDD18_PD"
	BITFLD.LONG 0x10 1.    "  VD28 , LDO_VDD28_PD"
	BITFLD.LONG 0x10 0.    "    BG , BG_PD"
TREE.END
TREE "2721"
SGROUP
	VARX 0x08 %l ADI.READ(0x8C44)
	TEXTLINE ""
	LINE.LONG 0x08 " DCDCCPU , DCDC_ARM_VOL"
	BITFLD.LONG 0x08 5.--9.   "  CTRL , DCDC_ARM0_CTRL"
	BITFLD.LONG 0x08 0.--4.   "  CAL , DCDC_ARM0_CAL"

	VARX 0x10 %l ADI.READ(0x8C1C)
	TEXTLINE ""
	LINE.LONG 0x10 " SW PD , POWER_PD_SW"
	BITFLD.LONG 0x10 10.   "  DCXO , LDO_DCXO_PD"
	BITFLD.LONG 0x10 9.    "   EMM , LDO_EMM_PD"
	TEXTLINE "                                "
	BITFLD.LONG 0x10 8.    " CLK6M , DCDC_TOPCLK6M_PD"
	BITFLD.LONG 0x10 7.    "   GEN , DCDC_GEN_PD"
	BITFLD.LONG 0x10 6.    "   MEM , DCDC_MEM_PD"
	TEXTLINE "                                "
	BITFLD.LONG 0x10 5.    "  CORE , DCDC_CORE_PD"
	BITFLD.LONG 0x10 4.    "   CPU , DCDC_ARM_PD"
	BITFLD.LONG 0x10 3.    "LDOMEM , LDO_MEM_PD"
	TEXTLINE "                                "
	BITFLD.LONG 0x10 2.    "  AV18 , LDO_AVDD18_PD"
	BITFLD.LONG 0x10 1.    "  VD28 , LDO_VDD28_PD"
	BITFLD.LONG 0x10 0.    "    BG , BG_PD"

TREE.END

TREE "PMIC SLP SETTING"
TREE "2731"
SGROUP "Sleep"
	VARX 0x1C %l ADI.READ(0x8DF0)
	TEXTLINE ""
	LINE.LONG 0x1C " SLP CTRL , SLP_CTRL"
	BITFLD.LONG 0x1C 3.    " XTL , LDO_XTL_EN: LDO and DCDC can be controlled by external device if this bit is set"
	BITFLD.LONG 0x1C 2.    "  LP , SLP_BG_LP_EN: Bandgap low power mode enable in deep sleep mode"
	BITFLD.LONG 0x1C 1.    "  IO , SLP_IO_EN: IO PAD sleep enable in deep sleep mode"
	BITFLD.LONG 0x1C 0.    "  PD , SLP_LDO_PD_EN: All LDO and DCDC power down enable in deep sleep mode"

	VARX 0x20 %l ADI.READ(0x8DF4)
	TEXTLINE ""
	LINE.LONG 0x20 " SLP DCDC , SLP_DCDC_PD_CTRL"
	BITFLD.LONG 0x20 9.    "    GPU_PD , SLP_DCDCGPU_PD_EN"
	BITFLD.LONG 0x20 8.    "  GPU_DROP , SLP_DCDCGPU_DROP_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x20 7.    " CORE_DROP , SLP_DCDCCORE_DROP_EN"
	BITFLD.LONG 0x20 6.    "     RF_PD , SLP_DCDCRF_PD_EN"
	BITFLD.LONG 0x20 3.    "    WPA_PD , SLP_DCDCWPA_PD_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x20 2.    "   ARM0_PD , SLP_DCDCARM0_PD_EN"
	BITFLD.LONG 0x20 1.    "   ARM1_PD , SLP_DCDCARM1_PD_EN"
	BITFLD.LONG 0x20 0.    "    MEM_PD , SLP_DCDCMEM_PD_EN"

	VARX 0x24 %l ADI.READ(0x8DF8)
	TEXTLINE ""
	LINE.LONG 0x24 " SLP LDO0 , SLP_LDO_PD_CTRL0"
	BITFLD.LONG 0x24 15.    "         RF0 , SLP_LDORF0_PD_EN"
	BITFLD.LONG 0x24 14.    "    EMMCCore , SLP_LDOEMMCCORE_PD_EN"
	BITFLD.LONG 0x24 13.    "        DCXO , SLP_LDODCXO_PD_EN"
	BITFLD.LONG 0x24 12.    "      WIFIPA , SLP_LDOWIFIPA_PD_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x24 11.    "       VDD28 , SLP_LDOVDD28_PD_EN"
	BITFLD.LONG 0x24 10.    "      SDCORE , SLP_LDOSDCORE_PD_EN"
	BITFLD.LONG 0x24 9.     "        SDIO , SLP_LDOSDIO_PD_EN"
	BITFLD.LONG 0x24 8.     "       USB33 , SLP_LDOUSB33_PD_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x24 7.     "      CAMMOT , SLP_LDOCAMMOT_PD_EN"
	BITFLD.LONG 0x24 6.     "       CAMIO , SLP_LDOCAMIO_PD_EN"
	BITFLD.LONG 0x24 5.     "       CAMD0 , SLP_LDOCAMD0_PD_EN"
	BITFLD.LONG 0x24 4.     "       CAMD1 , SLP_LDOCAMD1_PD_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x24 3.     "       CAMA0 , SLP_LDOCAMA0_PD_EN"
	BITFLD.LONG 0x24 2.     "       CAMA1 , SLP_LDOCAMA1_PD_EN"
	BITFLD.LONG 0x24 1.     "        VLDO , SLP_VLDO_PD_EN"
	BITFLD.LONG 0x24 0.     "        SIM1 , SLP_LDOSIM1_PD_EN"

	VARX 0x28 %l ADI.READ(0x8DFC)
	TEXTLINE ""
	LINE.LONG 0x28 " SLP LDO1 , SLP_LDO_PD_CTRL1"
	BITFLD.LONG 0x28 3.     "         CON , SLP_LDOCON_PD_EN"
	BITFLD.LONG 0x28 2.     "        SIM0 , SLP_LDOSIM0_PD_EN"
	BITFLD.LONG 0x28 1.     "      AVDD18 , SLP_LDOAVDD18_PD_EN"
	BITFLD.LONG 0x28 0.     "        SRAM , SLP_LDOSRAM_PD_EN"


	VARX 0x2C %l ADI.READ(0x8E3C)
	VARX 0x30 %l ADI.READ(0x8E40)
	VARX 0x34 %l ADI.READ(0x8E44)
	VARX 0x38 %l ADI.READ(0x8E48)
	TEXTLINE ""
	LINE.LONG 0x2C " XTL_EN0 , DCDC_XTL_EN0"
	BITFLD.LONG 0x2C 15.     "DCDC_CORE XTL0 , DCDC_CORE_EXT_XTL0_EN"
	BITFLD.LONG 0x2C 14.     " XTL1 , DCDC_CORE_EXT_XTL1_EN"
	BITFLD.LONG 0x2C 13.     " XTL2 , DCDC_CORE_EXT_XTL2_EN"
	BITFLD.LONG 0x2C 12.     " XTL3 , DCDC_CORE_EXT_XTL3_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x2C 3.     " DCDC_GPU XTL0 , DCDC_GPU_EXT_XTL0_EN"
	BITFLD.LONG 0x2C 2.     " XTL1 , DCDC_GPU_EXT_XTL1_EN"
	BITFLD.LONG 0x2C 1.     " XTL2 , DCDC_GPU_EXT_XTL2_EN"
	BITFLD.LONG 0x2C 0.     " XTL3 , DCDC_GPU_EXT_XTL3_EN"
	LINE.LONG 0x30 " XTL_EN1 , DCDC_XTL_EN1"
	BITFLD.LONG 0x30 15.     "DCDC_ARM0 XTL0 , DCDC_ARM0_EXT_XTL0_EN"
	BITFLD.LONG 0x30 14.     " XTL1 , DCDC_ARM0_EXT_XTL1_EN"
	BITFLD.LONG 0x30 13.     " XTL2 , DCDC_ARM0_EXT_XTL2_EN"
	BITFLD.LONG 0x30 12.     " XTL3 , DCDC_ARM0_EXT_XTL3_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x30 3.     "DCDC_ARM1 XTL0 , DCDC_ARM1_EXT_XTL0_EN"
	BITFLD.LONG 0x30 2.     " XTL1 , DCDC_ARM1_EXT_XTL1_EN"
	BITFLD.LONG 0x30 1.     " XTL2 , DCDC_ARM1_EXT_XTL2_EN"
	BITFLD.LONG 0x30 0.     " XTL3 , DCDC_ARM1_EXT_XTL3_EN"
	LINE.LONG 0x34 " XTL_EN2 , DCDC_XTL_EN2"
	BITFLD.LONG 0x34 15.     " DCDC_MEM XTL0 , DCDC_MEM_EXT_XTL0_EN"
	BITFLD.LONG 0x34 14.     " XTL1 , DCDC_MEM_EXT_XTL1_EN"
	BITFLD.LONG 0x34 13.     " XTL2 , DCDC_MEM_EXT_XTL2_EN"
	BITFLD.LONG 0x34 12.     " XTL3 , DCDC_MEM_EXT_XTL3_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x34 3.     " DCDC_GEN XTL0 , DCDC_GEN_EXT_XTL0_EN"
	BITFLD.LONG 0x34 2.     " XTL1 , DCDC_GEN_EXT_XTL1_EN"
	BITFLD.LONG 0x34 1.     " XTL2 , DCDC_GEN_EXT_XTL2_EN"
	BITFLD.LONG 0x34 0.     " XTL3 , DCDC_GEN_EXT_XTL3_EN"
	LINE.LONG 0x38 " XTL_EN3 , DCDC_XTL_EN3"
	BITFLD.LONG 0x38 15.     "  DCDC_RF XTL0 , DCDC_RF_EXT_XTL0_EN"
	BITFLD.LONG 0x38 14.     " XTL1 , DCDC_RF_EXT_XTL1_EN"
	BITFLD.LONG 0x38 13.     " XTL2 , DCDC_RF_EXT_XTL2_EN"
	BITFLD.LONG 0x38 12.     " XTL3 , DCDC_RF_EXT_XTL3_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x38 3.     " DCDC_WPA XTL0 , DCDC_WPA_EXT_XTL0_EN"
	BITFLD.LONG 0x38 2.     " XTL1 , DCDC_WPA_EXT_XTL1_EN"
	BITFLD.LONG 0x38 1.     " XTL2 , DCDC_WPA_EXT_XTL2_EN"
	BITFLD.LONG 0x38 0.     " XTL3 , DCDC_WPA_EXT_XTL3_EN"
TREE.END

TREE "2721"
SGROUP "Sleep"
	VARX 0x1C %l ADI.READ(0x8D98)
	TEXTLINE ""
	LINE.LONG 0x1C " SLP CTRL , SLP_CTRL"
	BITFLD.LONG 0x1C 2.    " XTL , LDO_XTL_EN: LDO and DCDC can be controlled by external device if this bit is set"
	BITFLD.LONG 0x1C 1.    "  IO , SLP_IO_EN: IO PAD sleep enable in deep sleep mode"
	BITFLD.LONG 0x1C 0.    "  PD , SLP_LDO_PD_EN: All LDO and DCDC power down enable in deep sleep mode"

	VARX 0x20 %l ADI.READ(0x8D9C)
	TEXTLINE ""
	LINE.LONG 0x20 " SLP DCDC , SLP_DCDC_PD_CTRL"
	BITFLD.LONG 0x20 3.    " CORE_DROP , SLP_DCDCCORE_DROP_EN"
	BITFLD.LONG 0x20 2.    "    WPA_PD , SLP_DCDCWPA_PD_EN"
	BITFLD.LONG 0x20 1.    "    ARM_PD , SLP_DCDCARM_PD_EN"
	BITFLD.LONG 0x20 0.    "    MEM_PD , SLP_DCDCMEM_PD_EN"

	VARX 0x24 %l ADI.READ(0x8DA0)
	TEXTLINE ""
	LINE.LONG 0x24 " SLP LDO0 , SLP_LDO_PD_CTRL0"
	BITFLD.LONG 0x24 14.    "        RF15 , SLP_LDORF15_PD_EN"
	BITFLD.LONG 0x24 13.    "        RF18 , SLP_LDORF18_PD_EN"
	BITFLD.LONG 0x24 12.    "    EMMCCore , SLP_LDOEMMCCORE_PD_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x24 11.    "        DCXO , SLP_LDODCXO_PD_EN"
	BITFLD.LONG 0x24 10.    "      WIFIPA , SLP_LDOWIFIPA_PD_EN"
	BITFLD.LONG 0x24 9.     "       VDD28 , SLP_LDOVDD28_PD_EN"
	BITFLD.LONG 0x24 8.     "      SDCORE , SLP_LDOSDCORE_PD_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x24 7.     "        SDIO , SLP_LDOSDIO_PD_EN"
	BITFLD.LONG 0x24 6.     "       USB33 , SLP_LDOUSB33_PD_EN"
	BITFLD.LONG 0x24 5.     "      CAMMOT , SLP_LDOCAMMOT_PD_EN"
	BITFLD.LONG 0x24 4.     "       CAMIO , SLP_LDOCAMIO_PD_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x24 3.     "        CAMD , SLP_LDOCAMD_PD_EN"
	BITFLD.LONG 0x24 2.     "        CAMA , SLP_LDOCAMA_PD_EN"
	BITFLD.LONG 0x24 1.     "        SIM2 , SLP_LDOSIM2_PD_EN"
	BITFLD.LONG 0x24 0.     "        SIM1 , SLP_LDOSIM1_PD_EN"

	VARX 0x28 %l ADI.READ(0x8DA4)
	TEXTLINE ""
	LINE.LONG 0x28 " SLP LDO1 , SLP_LDO_PD_CTRL1"
	BITFLD.LONG 0x28 3.     "         CON , SLP_LDOCON_PD_EN"
	BITFLD.LONG 0x28 2.     "        SIM0 , SLP_LDOSIM0_PD_EN"
	BITFLD.LONG 0x28 1.     "      AVDD18 , SLP_LDOAVDD18_PD_EN"
	BITFLD.LONG 0x28 0.     "        MEM , SLP_LDOMEM_PD_EN"


	VARX 0x2C %l ADI.READ(0x8DE4)
	VARX 0x30 %l ADI.READ(0x8DE8)
	VARX 0x34 %l ADI.READ(0x8DEC)
	TEXTLINE ""
	LINE.LONG 0x2C " XTL_EN0 , DCDC_XTL_EN0"
	BITFLD.LONG 0x2C 15.     "DCDC_CORE XTL0 , DCDC_CORE_EXT_XTL0_EN"
	BITFLD.LONG 0x2C 14.     " XTL1 , DCDC_CORE_EXT_XTL1_EN"
	BITFLD.LONG 0x2C 13.     " XTL2 , DCDC_CORE_EXT_XTL2_EN"
	BITFLD.LONG 0x2C 12.     " XTL3 , DCDC_CORE_EXT_XTL3_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x2C 3.     " DCDC_WPA XTL0 , DCDC_WPA_EXT_XTL0_EN"
	BITFLD.LONG 0x2C 2.     " XTL1 , DCDC_GPU_EXT_XTL1_EN"
	BITFLD.LONG 0x2C 1.     " XTL2 , DCDC_GPU_EXT_XTL2_EN"
	BITFLD.LONG 0x2C 0.     " XTL3 , DCDC_GPU_EXT_XTL3_EN"
	LINE.LONG 0x30 " XTL_EN1 , DCDC_XTL_EN1"
	BITFLD.LONG 0x30 15.     " DCDC_ARM XTL0 , DCDC_ARM_EXT_XTL0_EN"
	BITFLD.LONG 0x30 14.     " XTL1 , DCDC_ARM0_EXT_XTL1_EN"
	BITFLD.LONG 0x30 13.     " XTL2 , DCDC_ARM0_EXT_XTL2_EN"
	BITFLD.LONG 0x30 12.     " XTL3 , DCDC_ARM0_EXT_XTL3_EN"
	LINE.LONG 0x34 " XTL_EN2 , DCDC_XTL_EN2"
	BITFLD.LONG 0x34 15.     " DCDC_MEM XTL0 , DCDC_MEM_EXT_XTL0_EN"
	BITFLD.LONG 0x34 14.     " XTL1 , DCDC_MEM_EXT_XTL1_EN"
	BITFLD.LONG 0x34 13.     " XTL2 , DCDC_MEM_EXT_XTL2_EN"
	BITFLD.LONG 0x34 12.     " XTL3 , DCDC_MEM_EXT_XTL3_EN"
	TEXTLINE "                                "
	BITFLD.LONG 0x34 3.     " DCDC_GEN XTL0 , DCDC_GEN_EXT_XTL0_EN"
	BITFLD.LONG 0x34 2.     " XTL1 , DCDC_GEN_EXT_XTL1_EN"
	BITFLD.LONG 0x34 1.     " XTL2 , DCDC_GEN_EXT_XTL2_EN"
	BITFLD.LONG 0x34 0.     " XTL3 , DCDC_GEN_EXT_XTL3_EN"
TREE.END


TREE.END
TREE.END

TREE.END
